The present invention relates to a method of manufacturing a trench gate type field effect transistor which accommodates miniaturization.
MOS type LSIs using silicon substrates are currently in a phase where LSIs with a 0.18-μm design rule (design criterion) have shifted into mass production, but further improvements in the degree of integration, through miniaturization, are desired, and LSIs with 0.13-μm to 0.10-μm design rules are under development. Higher operating speeds and lower power consumption are also desired in these LSIs.
When an LSI is miniaturized and the degree of integration is made larger in scale, suppressing the short channel effect becomes an extremely important issue in reducing deviations in the performance of the individual transistors.
To suppress the short channel effect, in MOS type field effect transistors which are already put to practical use and in which a gate is formed on a semiconductor substrate, and a source and a drain are formed in a self-aligned manner with respect to the gate, attempts to optimize the impurity concentrations or shapes of the source and the drain, well impurity profiles in a channel area and the like are being made, and further, forming an impurity area, commonly referred to as a halo or a pocket, of an opposite conductivity type at an end of the source or the drain through methods such as oblique ion implantation or the like, and suppressing the short channel effect are being attempted.
In addition, for the suppression of the short channel effect, forming the source and the drain shallow while maintaining the low resistivities of the source and the drain becomes a fundamental and important factor.
Conventionally, the activation of impurities introduced into a semiconductor substrate to form a source and a drain is performed through a thermal treatment (900 to 950° C., 20 to 30 minutes) using a resistance heating furnace. In recent years, however, in order to form the source and the drain shallow and low in resistance by preventing impurity diffusion due to this thermal treatment, RTA (Rapid Thermal Annealing) using a halogen lamp is being performed.
In FIG. 3, a typical temperature increase-decrease profile of RTA is shown. In RTA, it rises to an annealing temperature of 1000 to 1100° C. at a rate of rise in temperature of 50 to 100° C., this annealing temperature is maintained for approximately 10 seconds, and natural cooling is performed.
In FIG. 4A to FIG. 4H, a method of manufacturing a typical n-type field effect transistor 100X, in which junctions of a source and a drain are formed using RTA, is shown. In this method, first, element separators 2 are formed in a p-type silicon substrate 1, and a through-film 3 comprising SiO2 or the like is formed (FIG. 4A), and ions are implanted as per the arrows through the through-film 3 to form a well 4 and a Vth adjusting layer (not shown) (FIG. 4B). Next, the through-film 3 is removed, and a gate insulating film 5 of approximately 3 to 5 nm is formed through thermal oxidation of 1000° C. and approximately 30 minutes. A polysilicon 6 with a thickness of approximately 500 nm and doped with phosphorus at a high concentration is deposited thereon through low-pressure CVD or the like. Approximately 300 nm of WSi 7 is deposited thereon through the CVD method to reduce gate resistance (FIG. 4C).
Then, a gate pattern with a desired design rule is formed using lithography technology and etching technology. With this gate pattern as a mask, approximately 1×1015 cm−2 of impurities such as arsenic, which become an extended source 8a and an extended drain 8b, are ion implanted at 10 keV as per the arrows (FIG. 4D). Next, an SiO2 film is deposited by normal CVD and a side wall 9 is formed by performing anisotropic etching. By performing ion implantation again, approximately 3×1015 cm−2 of arsenic, which forms an impurity introduced layer which is to become a source S and a drain D, is introduced at 30 keV (FIG. 4E).
Next, in order to form a pocket (halo) 10 for suppressing the short channel effect, approximately 1×1013 cm−2of a p-type impurity is ion-implanted at an angle of 10° to 30° with respect to the normal to the substrate surface at 20 keV (FIG. 4F). Then, in order to activate the impurities introduced into the substrate 1 up to this point, annealing of 1050° C. and approximately 10 seconds is performed by RTA using a halogen lamp.
Thereafter, an interlayer insulating film 11 of SiO2 or the like is deposited with the CVD method (FIG. 4G). Next, lead electrodes 14 of the source and the drain are formed in the interlayer insulating film 11 to obtain the transistor 100X (FIG. 4H).
However, even when RTA is used for the formation of the junctions of the source and the drain as described above, because cooling through natural radiation is performed after the annealing temperature has been maintained, the rate of fall in temperature during cooling cannot be controlled, and the profile due to the diffusion of the impurities during the fall in temperature presents a problem.
To this end, as shown in FIG. 5, methods such as spike RTA which takes the maintaining time at the annealing temperature to be zero, or quick cooling RTA, in which He gas or the like is used to force cool during the fall in temperature, are adopted.
However, even when these methods are utilized fully, the depth of the junctions and the resistance values of the source and the drain do not reach the values demanded of transistors with a gate length of 130 nm or below in the road map (ITRS '99) in the engineering community as shown in FIG. 6.
In addition, if RTA is performed when an impurity is introduced through ion implantation, point defects, such as numerous interstitial atoms or holes formed due to crystal damage from the impact of the ions, cause enhanced diffusion at the initial stage of the thermal treatment of RTA. Thus, while redistribution of the impurities due to normal thermal diffusion is suppressed considerably, diffusion of the impurities accompanying the enhanced diffusion of the point defects occurs, and the impurity profile causes a significant redistribution.
As such, as an activation method for the impurities, annealing using excimer laser is being considered. In the annealing with excimer laser, since the temperature rises to 1000° C. or higher in an extremely short period of time of several nanoseconds, the impurities can be activated without any accompanying enhanced diffusion. In FIG. 7, the relationship between the depth of junction, the surface resistivity (ohm/square) and the laser energy density (mJ/cm2) of a p+ layer, in which BF2 (15 KeV and 3×1015 cm−2) is implanted and which is activated with a XeCl excimer laser (a wavelength of 308 nm and a pulse width of 40 nsec), is shown.
In the annealing with excimer laser, since heating is performed in an extremely short period of time, the annealing treatment is performed in a thermally nonequilibrium state. Therefore, as compared with the case where annealing is performed through RTA, forming a shallow and low-resistance junction becomes possible as shown in FIG. 7. However, with the excimer laser, there are cases where a gate thermally insulated from a semiconductor substrate by a gate insulating film reaches a temperature exceeding the melting point of the base material thereof during annealing, and deformation or breakage is brought about due to melting.
To address such a problem, a selective annealing method for performing thermal treatment only on desired sections such as a source and a drain is needed.
As a selective annealing method, there is a method in which, making use of the fact that the reflectance of a laser varies depending on the thickness of a Si oxide film, Si oxide films with different film thicknesses are formed on a material to be irradiated depending on the presence or absence of the necessity of a thermal treatment, and laser is irradiated. More specifically, for example, with respect to an excimer laser of a wavelength of 308 nm, the reflectance of a Si oxide film shows changes with respect to the film thickness of the Si oxide film as shown in FIG. 8. Therefore, in the selective excimer laser annealing method using an excimer laser, an Si oxide film is deposited with a film thickness of 50 nm, at which the reflectance is minimum, on a section in which thermal treatment is desired, and with a film thickness of 100 nm, at which the reflectance is maximum, on a section in which thermal treatment is not desired (H. Tsukamoto et al, Jpn. J. Appl. Phys. 32, L967 (1993)).
In FIG. 9A to FIG. 9I, a method of manufacturing a conventional n-type transistor, in which this selective excimer laser annealing method is used to activate impurities in a source and a drain, is shown. In this method, first, element separators 2 are formed in a p-type silicon substrate 1, a through-film 3 comprising SiO2 or the like is formed (FIG. 9A), and ions are implanted through the through-film 3 to form a well 4 and a Vth adjusting layer (not shown) (FIG. 9B). Next, the through-film 3 is removed, approximately 3 to 5 nm through thermal oxidation of 1000° C. and approximately 30 minutes. Thereon, a polysilicon 6 of a thickness of approximately 500 nm and doped with phosphorous at a high concentration is deposited through reduced-pressure CVD or the like. Approximately 300 nm of WSi 7 is deposited thereon through the CVD method to reduce gate resistance, and further, an Si oxide film 12a with a film thickness of 50 nm is deposited through LPCVD or the like (FIG. 9C).
Then, lithography technology and etching technology are used to form a gate pattern with a desired design rule (polysilicon 6/WSi 7/Si oxide film 12a). Then, with this gate pattern as a mask, approximately 1×1015 cm−2 of impurities such as arsenic, which become an extended source 8a and an extended drain 8b, are ion-implanted at 10 keV as per the arrows (FIG. 9D). Next, a side wall 9 is formed by depositing a SiO2 film with a normal CVD method and performing anisotropic etching. By implanting ions again, approximately 3×1015 cm−2 of arsenic which forms an impurity introduced layer which is to become a source S and a drain D is introduced at 30 keV (FIG. 9E).
Next, in order to form a pocket (halo) 10 for suppressing the short channel effect, approximately 1×1013 cm−2 of a p-type impurity is ion-implanted at an angle of 10° to 30° with respect to the normal to the substrate surface at 20 keV (FIG. 9F).
Then, as an anti-reflection film, an Si oxide film 12b is deposited with the CVD method and in a film thickness of 50 nm, at which excimer laser exhibits minimum reflectance. Thus, this Si oxide film 12b of a film thickness of 50 nm is formed on the impurity introduced layer which is to become the source S and the drain D, and on the gate pattern, Si oxide films of a total film thickness, from this Si oxide film 12b and the Si oxide film 12a deposited before the formation of the gate pattern, of 100 nm, in other words of a film thickness at which the reflectance of the excimer laser is maximum, are formed (FIG. 9G).
Next, to activate the impurities introduced into the substrate 1 up to this point, annealing is performed at an energy density of 900 to 1000 mJ/cm2 using an excimer laser L (FIG. 9H).
Thereafter, an interlayer insulating film 11 of SiO2 or the like is deposited with the CVD method, and subsequently, lead electrodes 14 of the source and the drain are formed in the interlayer insulating film 11 to obtain a transistor 100Y (FIG. 9I).
When the transistor 100Y is thus formed with the selective annealing method, because the source S and the drain D, of which the impurities should be activated, alone are heated to a high temperature without having the gate G heated to a high temperature, deformation or breakage of the gate G accompanying annealing can be prevented. In addition, since a thermally non-equilibrium laser annealing is performed in the source S and the drain D, a shallow and low-resistance junction can be formed. Thus, according to this method, it is possible to form a transistor which operates with a gate length of 0.1 μm or below (H. Tsukamoto et al, Jpn. J. Appl. Phys. 32, L967 (1993)).
In this method, however, because selective laser annealing is performed, the addition and the difficulty of the step accompanies in that the Si oxide films 12a and 12b must be uniformly formed with predetermined film thicknesses over the entire substrate surface before and after the formation of the gate pattern.
As described above, in the conventionally employed method using a resistance heating furnace or the method using RTA, in activating the impurities introduced into the substrate to form the source or the drain of the field effect transistor, it is difficult to form junctions of the source and the drain shallow and with low resistance to an extent that the short channel effect can be effectively suppressed in an extremely miniaturized transistor with a gate length of 0.1 μm or below.
In addition, when the selective laser annealing method is used, although it is possible to form junctions of the source and the drain shallow and with low resistance, the addition and the difficulty of the step are involved.
To this end, it is an object of the present invention to provide a new method of manufacturing a field effect transistor which forms an extremely miniaturized field effect transistor with junctions of a source and a drain shallow, with low resistance and with a simple process to an extent that the short channel effect can be effectively suppressed.